The PPE processes SIMD operations in the VXU within its PPU. The operations are those of the Vector/SIMD Multimedia Extension instruction set.
The SPEs process SIMD operations in their SPU. The operations are those of the SPU instruction set.
| Feature | PPE | SPE |
|---|---|---|
| Number of SIMD registers | 32 (128-bit) | 128 (128-bit) |
| Organization of register files | separate fixed-point, floating-point, and vector registers | unified |
| Load latency | variable (cache) | fixed |
| Addressability | 2⁶⁴ bytes | 256-KB local store |
| Instruction set | more orthogonal | optimized for single-precision float |
| Single-precision | IEEE 754-1985 | extended range |
| Doubleword | no doubleword SIMD | double-precision floating-point SIMD |