Example 1: Tuning SPE performance with static and dynamic timing analysis

  1. Static analysis of SPE threads
    The listing below shows an spu-timing static timing analysis for the inner loop of the SPE code.
  2. Dynamic analysis of SPE threads
    The listing below shows a dynamic timing analysis on the same SPE inner loop using the IBM Full System Simulator for the Cell Broadband Engine.
  3. Optimizations
    To eliminate stalls and improve the CPI — and ultimately the performance — the compiler needs more instructions to schedule, so that the program does not stall. The SPE's large register file allows the compiler or the programmer to unroll loops.
  4. Static analysis of optimization
    The listing below shows a spu_timing static timing analysis for the optimized SPE thread (process _buffer subroutine only).
  5. Dynamic analysis of optimizations
    The listing below shows a dynamic timing analysis on the IBM Full System Simulator for the Cell Broadband Engine for the optimized SPE thread (process buffer only). It shows that 78 registers are used, so the used percentage is 60.94.
Parent topic: Performance analysis
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