Move
move{.size} src,dst
- The destination (dst) operand must be a "data alterable mode" (it cannot be an A register, an immediate operand (#const), or a PC-relative address).
- "size" can be b or w or l i.e. byte, word, longword
- Action - copies the value in source to the destination
move.b D2,D3
move.w (A2)+,45(A1)
move.l #23456,-(SP)Movea (move into A register)
movea{.w or .l} src,Ai
- In machine language, this is identical to "move". There is really no restriction that says "dst" can't be an A register. Simulator doesn't care if you use "movea" or "move", but other assemblers might.
- If no size is specified, ".w" is assumed. That will usually be a disaster. ALWAYS PUT THE ".L" ON IT!
movea.l A4,A3 ;Ptr1:=Ptr2
movea.l 4(A2),A2 ;Ptr:=Ptr^.LinkMoveq (move quick)
moveq #small,Di
- Very restricted: The source operand must use immediate mode, and only with an 8-bit signed integer constant (-128..127). The destination must be a D register.
- The constant is sign-extended and fills the entire D register
- No size is allowed (not moveq.w or moveq.b).
- So why not just use "move #7,D3" instead of "moveq #7,D3"?
- When you can use it, moveq is faster.
- The machine language instruction is 2 bytes, not 6 bytes.
moveq #5,D3
The subtraction instructions are identical to the add instructions. Just change "add" to "sub" in all of the instructions below.
Add
add{.size} src,dst
- The destination (dst) operand must be a "data alterable mode" (it cannot be an A register, an immediate operand (#const), or a PC-relative address).
- One of the two operands must be a D register
- If this is a problem, use one of the specialized instructions that follow.
add.b D2,D3
add.w (A2)+,D4
add.l D4,16(A3)Adda (Add to A register)
adda{.w or .l} src,Ai
- This time "adda" and "add" are really different, even in machine language, and you must use the right one.
- If no size is specified, ".w" is assumed. That will usually be a disaster. ALWAYS PUT THE ".L" ON IT!
adda.l #16,A4 ;Advance a pointer by 16 bytes
adda.l D4,A3 ;Add a calculated amount to A3
adda.l 46(A2),A3 ;Unlikely, but legalAddi (Add immediate)
addi{.size} #const,dst
- The destination (dst) operand must be a "data alterable mode" (it cannot be an A register, an immediate operand (#const), or a PC-relative address).
addi.l #16,(A4) ;add or adda can't do this
addi.w #1,Count ;Count:=Count+1Addq (add quick)
addq{.size} #verysmall,dst
- The source operand must use immediate mode, and only with a small positive constant between 1 and 8 inclusive.
- The destination (dst) operand cannot be an immediate operand (#const), or a PC-relative address) (but an A register is OK).
- A size is allowed (unlike moveq).
- So why not just use "add #7,D3" instead of "addq #7,D3"?
- When you can use it, addq is much faster.
- The machine language instruction is only 2 bytes (the opcode only).
addq.w #1,D3 ;Fastest way to increment D3
addq.l #8,A3 ;Can even add to an A register
addq.b #1,Code ;or memory
lea <ea>,Ai
The first operand (<ea> or "effective address") must refer directly to an address in memory. It cannot be Di, Ai, (Ai)+, -(Ai), or #const. But no memory access is done. Instead, the address that would have been used by a normal instruction (move, add, etc.) is placed in Ai.
lea Junk,A3 ;Put the address Junk into A3 (right)
movea.l #Junk,A3 ;Put the address Junk into A3 (wrong)
Under "normal" conditions, the above two instructions would accomplish the same thing. However, due to "relocatability" in real-life systems (Mac + MAS), the second one will generate an error message. Always use the first one.
clr{.size} dst
Clears the destination to 0. The destination (dst) operand must be a "data alterable mode" (it cannot be an A register, an immediate operand (#const), or a PC-relative address).
clr.w D3 ;Initialize D3 to 0
clr.l Count ;Initialize Count to 0
clr.w (A4)+ ;Clear the next word in the array
neg{.size} dst
Negates the destination (twos complements it). The destination (dst) operand must be a "data alterable mode" (it cannot be an A register, an immediate operand (#const), or a PC-relative address).
neg.w D3 ;Negate D3
neg.l X ;Negate X
neg.w (A4)+ ;Negate the next word in the array
jsr addresss
This is not a complete description of this instruction. That will be done later. For now, we will only use it to call built-in library routines (for things such as I/O).
jsr stop ;terminate this program
jsr decin ;read in a decimal number
jsr strout ;write out a character string
The compare instructions are almost identical to the subtract instructions (which are the same as the add instructions above). Just change "add" to "cmp" in all of the instructions above, with the following exceptions:
Compare instructions are the same as subtract instructions in their operation, except that the result of the calculation is discarded. The only purpose is to set the condition code. Following a compare instruction, you almost always find a conditional branch.
cmp.w D2,D3 ;perform D3-D2, set CC reg, discard result
cmpi.b #'0',D4 ;compare D4 to the ascii code for '0'
cmpa.l A2,A3 ;compare two pointers in A2 and A3 (A3-A2)
cmp.w D3,#10 ;WRONG!!
cmp.w #10,D3 ;RIGHT!!
Z-it is set(i.e. made 1) if the result is 0, otherwise it is cleared (made 0) N-it is cleared if result is negative, otherwise it is cleared V-it is cleared if there is an overflow i.e. the number is too large to be stored and is cleared otherwise C-it is cleared if there is a borrow or carry out of the top bit (overflow for unsigned integers) otherwise it is cleared. More on these flags later.Unconditional Branch BRA PLACE works like a "go to". The instruction at PLACE will be the next one to be executed. Conditional Branches BEQ PLace If result is 0, then execute instruction at PLACE otherwise execute next instruction. BNE PLACE If result is not 0, then ... instruction BLT PLACE If result < 0, then ... instruction BLE PLACE If result <= 0, then ... instruction BGT PLACE If result > 0, then ... instruction BGE PLACE If result >= 0, then ... instructionMultiplication
MULU,Dn Unsigned Multiplication MULS ,Dn Signed Multiplication Action - multiplies two 16 bit operands, yielding a 32 bit operand stored in Dn. No carry or overflow is possible Division
DIVUNotes,Dn Unsigned Division DIVS (ea>,Dn Signed Division Action - Divide the 32 bit destination operand (right side) by the 16 bit source operand and store the qutient in LSW of the destination and the remainder in the MSW of the destination.
- Division by 0 generates an exception and usually stops the program with an error.
- Overflow is possible and detected. No operation occurs. When does this happen and does the simulator do this really?
- In signed division the sign of the remainder is always the same as the sign of the dividend unless the remainder is 0.
Swap Instruction
Swap Dn causes the contents of MSW and LSW to be interchanged.Test Intruction
TST.{size}checks the value in and sets the Z and N flags.