CPU Hardware Model - Registers


General Purpose Registers:

Special Purpose Registers: (available to programmer)

Registers A5 and A6 are general purpose registers as far as the hardware or CPU is concerned, but there are software conventions which give them special meaning (as the global pointer and the frame pointer). Do not use them!

There are other registers in the CPU, but these are not visible to the assembly language (or machine language) programmer, and are implementation-dependent.


D3.B means the LSB of D3 (least significant byte)
D3.W means the LSW of D3 (least significant word)
D3.L means all 32 bits of D3

When an instruction affects Di.B or Di.W or Ai.W the upper portion of the register is unaffected.

Example: The instruction
causes D3.B <- D4.B + D3.B and so might have the following affect:

       D4: 123456FF     LSB is    FF
   old D3: 12345678     LSB is    78
           --------            -----
   new D3: 12345677     sum is (1)77 [Carry (1)-> C bit of CC in SR]


General Purpose Registers:

%g0...%g7 "global" registers (registers 0..7)
%o0...%o7 "output" registers (registers 8..15)
%L0..%L7 "local" registers (registers 16..23)
%i0..%i7 "input" registers (registers 24..31)

Special Purpose Registers:

Some registers are also special by software convention (as in the 680x0) and should not be used. These are %i6, %i7, %o6, %o7, and %g2..7. Don't use these. In general, use the local registers first, then %i0..%i5, then %o2..%o5 and %g1.

In the SPARC, all 32 bits of a register are always used for any operation.