CPU Hardware Model - Registers
General Purpose Registers:
- D0...D7 Eight 32-bit registers primarily for Data
- A0...A7 Eight 32-bit registers primarily for Addresses
- Register A7 has special properties built into the hardware, and is
known as SP (the Stack Pointer). (Actually, there may be 2 or 3 different
A7 registers, but only one is visible to user programs.)
Special Purpose Registers: (available to programmer)
- PC (Program Counter) holds the address of the next instruction to be
executed. This is a 32-bit register (SPARC, 68020+) which gives a 4GB address
space, or a 24-bit register (68000 - obsolete - allows addressing of only
a 16MB address space).
- SR (Status Register) is a 16-bit register with many small fields within
it. At the moment, only the condition code (CC) bits (named X N Z V C)
are important. (Sometimes the Condition Code Register (CCR) is referred
to, but it is not a separate register - it is a 5-bit field in the SR.)
This is where the overflow is recorded.
Registers A5 and A6 are general purpose registers as far as the hardware
or CPU is concerned, but there are software conventions which give
them special meaning (as the global pointer and the frame pointer). Do
not use them!
There are other registers in the CPU, but these are not visible to the
assembly language (or machine language) programmer, and are implementation-dependent.
- D3.B means the LSB of D3 (least significant byte)
- D3.W means the LSW of D3 (least significant word)
- D3.L means all 32 bits of D3
When an instruction affects Di.B or Di.W or Ai.W the upper portion of
the register is unaffected.
Example: The instruction
causes D3.B <- D4.B + D3.B and so might have the following affect:
D4: 123456FF LSB is FF
old D3: 12345678 LSB is 78
new D3: 12345677 sum is (1)77 [Carry (1)-> C bit of CC in SR]
General Purpose Registers:
- %r0...%r31 are 32 32-bit registers
- However, don't use these names! They fall into four groups which
behave differently when subprograms are used, and they have the following
names to reflect this:
- %g0...%g7 "global" registers (registers 0..7)
- %o0...%o7 "output" registers (registers 8..15)
- %L0..%L7 "local" registers (registers 16..23)
- %i0..%i7 "input" registers (registers 24..31)
- Register %g0 is extremely special. It is always equal to 0 (00...00)
and any attempts to change it are ignored.
Special Purpose Registers:
- PC (Program Counter) - address of the instruction being executed
- nPC (next Program Counter) - address of the next instruction to be
- %y - special register used only for multiplication and division
- PSR (Processor State Register) - like the SR in the 680x0. Also contains
the integer condition code (iCC), but only 4 bits (N Z V C). One of
these is overflow bit.
Some registers are also special by software convention (as in the 680x0)
and should not be used. These are %i6, %i7, %o6, %o7, and %g2..7. Don't
use these. In general, use the local registers first, then %i0..%i5,
then %o2..%o5 and %g1.
In the SPARC, all 32 bits of a register are always used for any