May 1st: Project Report 3
April 11th: Project Report 2
Problem Statement:
Data dependencies limit instruction-level parallelism (ILP) in EPIC/VLIW processors. These dependencies are often caused by an ambiguous memory dependency between a load and a store, or between two stores, where it cannot be determined if the instructions involved access overlapping memory locations. To eliminate these dependencies an advanced load allows a load to be moved above a store even if it is not known whether the load and the store may reference overlapping memory locations. Below is a simple example*:
Original Code:
st8 [r4] = r12 // ambiguous store
ld8 r6 = [r8] ;; // load to advance
add r5 = r6, r7
st8 [r18] = r5
Speculative Code:
ld8.a r6 = [r8] ;; // advance load
add r5 = r6, r7
st8 [r4] = r12
chk.a r6, recover // check advance load
back:
st8 [r18] = r5
. . . . .
. . . . .
recover:
ld8 r6 = [r8] ;;
add r5 = r6, r7
br back:
Objective:
In this work, we will dynamically profile code to identify speculative loads that are predominantly incorrect and remove such loads as the program executes.