Parallel Thread Execution ISA was developed and utilized in the backend for GPGPU kernel compilation. While this platform is useful for efficient code optimization as well as hardware portability, it also presents the opportunity to more efficiently add GPGPU extensions to existing compilers/language extensions. The purpose of this development effort is to demonstrate the process and issues associated with adding PTX extensions to the backend of an existing compiler frontend/backend.

Following are links to further information and research concerning PTX and CUDA development.

CUDA Programming Toolkit

PTX ISA Specification

PTX Backend for LLVM

As mentioned in the PTX Backend features page the process to go from Pseudo language parsing to PTX is best accomplished by adding an additional step to the proposed list. The LLVM byte code used to generate PTX modules will start out as Jasmin assembly which is used to generate Java byte code. Below is a link to the VMKit project which is used to generate LLVM byte code from the compiled Java byte code.

VMKit for JVM and LLVM