Siegfried Benkner(Institute for Software Science, University of Vienna
), Thomas Brandes(Institute for Algorithms and Scientific Computing, German National Research Center for Information Technology (GMD)
)
To appear at (HIPS'01), San Francisco, California, USA, April 23, 2001
Abstract
This paper presents extensions of High Performance Fortran for clusters of
SMPs. By means of a small set of new language features, the hierarchical
structure of SMP clusters may be described. Based on this information,
compilers can adopt a hybrid parallelization strategy, combining distributed-
memory parallelism with shared-memory parallelism.
The concept of processor mappings is provided in order to define a mapping
of abstract processor arrays to abstract node arrays. Based on processor
mappings, the compiler can derive from usual data mappings an inter-node and
an intra-node data mapping. The inter-node data mapping controls distributed-
memory parallelization with respect to the nodes of a cluster, while the
abstract intra-node data mapping controls shared-memory parallelization within nodes.
Additional mechanisms are proposed for specifying inter- and intra-node
data mappings explicitly, for controlling specific shared-memory
parallelization issues, and for integrating OpenMP routines in HPF
applications.
The proposed features are being realized within the ADAPTOR and VFC compiler.
The parallelization strategy for clusters of SMPs adopted by these compilers is
discussed as well as a hybrid-parallel execution model based on a combination of
MPI and OpenMP. Early experimental results indicate the effectiveness of the
proposed features.
