PowerCap: HPC Power Modeling and Active Control

The overall objective of this work is to establish systematic support for power considerations as a first-order objective for HPC system. This includes all phases, i.e., planning, procurement, provisioning, and operations. It also spans from prototypical system software development across all layers to simulation-based modeling when hardware is not available yet. We leverage any available power knobs, such as DVFS, capping, gating. And we consider trends in manufacturing, such as processor variations resulting in different power profiles of multi-core packages, even if they originate from the same die and have identical manufacturer specifications. Hence, processors have a range of different power efficiencies.