Pipeline and Path analysis of Power-aware Embedded Architecture
CSC 714 Real Time Computer
Systems
-Kiran Seth
In Real-Time systems, it is critical to have guaranteed temporal and logical performance. Correct operation requires task deadlines to be met while maintaining correctness of the operation. As the deadlines of Real-Time system tighten, performance increasing techniques like caches, pipelining, branch prediction and out of order execution are added to embedded processors. These complex pipelines increase the performance of embedded processors, but it is difficult to guarantee the performance of a complex pipeline. The Worst Case Execution Time (WCET) for tasks is required for schedulability analysis and also for creating the schedules. The WCET is also useful in systems that perform frequency scaling. It is very difficult to accurately measure WCET of tasks on a complex pipeline. But for simple pipelines, it is possible to calculate the WCET accurately.
During the course of this project, a tool for performing path analysis of a program and providing its WCET for a simple pipeline will be modified, the parametric paradigm will be used for representing the execution characteristics in response to frequency scaling and methods for Power-aware path analysis will be investigated.
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