The analysis of how execution times for different cryptographic algorithms vary in the Atmega 128 processor forms the basis of this project. The results could be useful in the analysis of worst-case execution times that form an important discussion in determining the applicability of real-time systems.Security in Embedded systems is emerging as a growing issue in recent times. Limitations in processing power and communications bandwidth and the mismatch between wide arithmetic for security(32 bit word operations) and embedded data bus widths(8 or 16 bits) offer a great challenge in implementing encryption algorithms for embedded systems. The variability of execution times is of particular interest to Real Time systems. Variations of execution times in small embedded systems may be due to the software mechanisms used by the compiler to implement certain features that are not present, such as caches that are prevalent in a normal processor. The results that come out of the variability analysis can be valuable in the analysis of worst-case execution times suited for schedulability analysis in the context of real-time systems.
The cryptographic algorithms used are IDEA, SHA1, MD5, RC4 and RC5. These algorithms are quite simple and operations involve the addition of 8 bit elements or swapping variables in a 256-byte state table, or sometimes multiplications. They are quite simple algorithms and can be executed without any fuss on embedded architectures. The Atmega128 is at the high end of the AVR family’s performance spectrum. It is a RISC architecture featuring 8 bit native word size, 32 general purpose registers and support for 16 bit operations. It features a 2 stage pipeline and has a 2-cycle multiply instruction. The tools used are the avr-gcc for compilation of C to .hex format, and uisp to upload programs onto the processor. Results are read at the minicom via the serial port.
The following list refers to more details of the project, and the results obtained: