CSC 714 Project Proposal

Topic: 405LP power management

Tricia Glidewell (taglidew), Deepa Srinivasan(dsriniv)

Submitted on 10/18/05

Web page: http://www4.ncsu.edu/~dsriniv/csc714/index.html

Problem description

Energy consumption has become a vital design constraint in embedded systems. The demand for efficient energy management is critical in portable and embedded devices where the available battery service life is critical. It is also important in non-embedded systems so as to conserve energy consumed to bring down costs and also for accurate infrastructure support (for e.g., in a datacenter, the power consumed by several servers can impact the cooling needed for the room). Hence, it is an important field of study to enable efficient power management of devices, both embedded and otherwise. One of the main ideas in power management is to detect when a system is idle and scale down the power consumed in that state. When the system is at peak (or comparable), it is scaled back up so that the performance impact is kept minimum. Dynamic Voltage Scaling (DVS) is extensively supported in current processors so as to maximize battery life/minimize power consumption in various systems. Further, certain components of a system can also be set to different sleep or standby modes wherein they are completely inactive and hence do not consume any power (this is our understanding – need to verify if this applies to all “sleep modes”), thus reducing leakage power or power consumed in an idle state of the system. It is also our understanding that, with recent advances in manufacturing technology, leakage or static power dominates the power consumption in a system, rather than the power consumed when a device or system component is active. Hence, it is important to study this aspect of power management in detail.

In our project, we will use the PowerPC 405LP processor board – the 405LP is based on the PowerPC 405 processor core and also offers power efficiency through Dynamic Voltage Scaling (DVS). It also supports standby or (two different) sleep modes, as described above. The main goal of our project to study these sleep modes on the 405LP processor board. In particular, we are interested to determine the overhead of using/enabling the sleep modes – i.e. when a component in the system goes into a sleep mode, what is the time delay, from when it is needed to be active again to when it actually becomes active. This time delay will be important for real-time applications since it will need to be taken into account while determined task schedules (according to deadlines) and system idle time. A stretch goal for the project will be to integrate the sleep modes with a real-time scheduler.

Outline for this project

Below are the major milestones for our project.

1. The first step is to acquaint ourselves with the 405LP development board and development environment. This involves connecting to the board and running sample programs. We will also go through the relevant parts of the Linux kernel to understand the power management modifications done for the 405LP.

2. Next, or overlapping with item #1, we will read relevant current literature (that is reference below), to better understand the 405LP processor system as well as power management techniques.

3. We will then modify the DPM (or Dynamic Power Module) driver that is already available in the kernel. The modification is to enable a finer-grained timer than is presently available for measuring wake-up overhead. The modification may also be to enable the sleep modes of the processor (this is our understanding – we will have better information regarding this once we have completed milestone #1).

4. Next, we will implement an application program to exercise the driver and also include code in the driver to measure the wake-up time overhead for the different sleep modes.

5. As a stretch goal, if the above milestones are completed, we will attempt to incorporate the sleep modes in a real-time scheduler.

References

Below are the references that we have collected so far. Additional references will be added as we progress in our literature search.

[1] "Feedback EDF Scheduling Exploiting Hardware-Assisted Asynchronous Dynamic Voltage Scaling" by Y. Zhu and F. Mueller in ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'05), Jun 2005, pages 203-212.

[2] H. Aydin, R. Melhem, D. Mosse, and P. Mejia-Alvarez. Power-aware scheduling for periodic real-time tasks. IEEE Trans. Comput., 53(5):584–600, 2004.

[3] B. Brock and K. Rajamani. Dynamic power management for embedded systems. In IEEE International SOC Conference, Sept. 2003.

[4] A. Dudani, F. Mueller, and Y. Zhu. Energy-conserving feedback edf scheduling for embedded systems with realtime constraints. In ACM SIGPLAN Joint Conference Languages, Compilers, and Tools for Embedded Systems (LCTES’02) and Software and Compilers for Embedded Systems (SCOPES’02), pages 213-222, June 2002.

[5] IBM and MontaVisa Software. Dynamic power management for embedded systems. white paper.

[6] K. Nowka, G. Carpenter, and B. Brock. The design and application of the powerpc 405lp energy-ef_cient system on chip. IBM Journal of Research and Development, 47(5/6), September/November 2003.

[7] Y. Zhu and F. Mueller. Feedback edf scheduling exploiting dynamic voltage scaling. In IEEE Real-Time EmbeddedTechnology and Applications Symposium, pages 84.93, May 2004.

[8] P. Pillai and K. Shin. Real-time dynamic voltage scaling for low-power embedded operating systems. In Symposium on Operating Systems Principles, 2001. K. Govil, E. Chan, and H.Wasserman. Comparing algorithms for dynamic speed-setting of a low-power cpu. In 1st Int’l Conference on Mobile Computing and Networking, Nov 1995.

[9] R. Minerick, V. W. Freeh, and P. M. Kogge. Dynamic power management using feedback. In Proceedings of Workshop onCompilers and Operating Systems for Low Power, 2002.

[10] PowerPC 405LP user manual.