STATIC TIMING ANALYSIS OF
IBM POWERPC 750 CX
By
Gopi Rao
Amol
Kamble
INTRODUCTION:
For
any Real Time embedded system to meet its deadline, the Worst-Case execution time (WCET) of each task in the system should
be known. The Process of statically determining the WCET of a task is called Timing
Analysis. The scheduling decision of a task depends on its WCET and the
total time in the schedule. For real-life programs, finding the program run
that leads to WCET is impossible to achieve. What is achievable is computing an
upper bound of the WCET, i.e., a time greater than real but incomputable WCET.
This project is aimed at computing the WCET for IBM PowerPC 750 CX, which is
used in the Airbus A380. Hence computation of WCET of IBM PowerPC 750CX helps
in making effective scheduling decisions in such safety critical real time
systems, dynamically.
STATIC
TIMING ANALYSIS:
Schedulability tests in real time systems are generally based on the
assumption that the WCET of every task in the task set being scheduled is known
a priori. Static timing analyser propagates through all the execution paths in
a program and calculates a safe upper bound on the time for the longest path in
the program. The structure of a program may cause a hurdle in the path of the
analyzer due to factors like data dependent control flow, pointer accesses etc.
Some architectural features like data cache behavior can cause unpredictability
for a timing analyzer.
We can use the following frame work as an
analytical approach
to
compute the WCET bounds.
1.
The assembly code
generated (in our case, the PowerPC code) by the gcc cross-compiler is given as
input to the Pcompiler (Pseudo
Compiler) which creates the path files using Control Flow and Basic Block
information.
2.
The framework also has a
Static cache simulator that
simulates the cache.
3.
The resulting cache organization along with
the control flow information is fed into the Timing Analyzer which computes the safe bound WCET.
Proposed Milestones
1.
PCompiler
– Week ending 10/23/2005
1.
Static
Cache Simulator – Week ending 10/30/2005
2.
Timing
Analyzer – Week ending 11/20/2005
3.
Project
Report – Week ending 11/27/2005
References:
1.
"Bounding Worst-Case Instruction Cache Performance"
by R. Arnold, F. Mueller, D. B. Whalley and M. Harmon in
IEEE Real-Time Systems Symposium, Dec 1994, pages 172-181
http://moss.csc.ncsu.edu/~mueller/publications.html
#19
2.
"Bounding Worst-Case Data Cache Behavior by Analytically
Deriving Cache Reference Patterns" by H. Ramaprasad and F. Mueller in
Real-Time and Embedded Technology and Applications Symposium, March 2005, pages
148-157.(slides). http://moss.csc.ncsu.edu/~mueller/ftp/pub/mueller/papers/rtas05dcache.pdf
3.
“Computing the WCET of an Avionics
Program by Abstract Interpretation” by Jean Souyris, Erwan le Pavec, Guillaume
Himbert, Victor Jégu (Airbus France), Guillaume Borios (Atos Origin
Integration) and Reinhold Heckmann (AbsInt
http://artist.cs.uni-sb.de/WCET05/Papers/Souyris.pdf