Power management is an important design aspect of embedded systems design, especially for battery constrained devices. Various power optimization techniques have been proposed which offer power reduction while maintaining the safe operation of the system. Many processors support different power saving modes, but they involve lot of overhead for hard real-time systems. Recently many processors added support for Dynamic Power Management (DPM) techniques which allow power parameters to be changed even while a program is in execution.

Dynamic Voltage Scaling (DVS) and Dynamic Frequency Scaling (DFS) are the most widely deployed DPM techniques. But dynamic power management techniques when applied only to processor core can be of limited use. Latest technological advances in processor design has lead to the development of low-power processor cores. Power optimization on the already low power consuming processor core might not provide significant power savings. Internal/external bus and memory also consume significant power, sometimes even more than the processor itself. So voltage and frequency scaling can be expected to provide significant power optimization when applied to the internal/external bus and memory subsystem. The aim of this project would be to integrate DVS/DFS to the front side bus and memory subsystem and study the power optimizations that can be achieved on the IBM PowerPC 405LP board.