Security Techniques in Cyber Physical Systems
Christopher Zimmer
CSC 714
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Report 1 Proposal |
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Report 2 Midterm Proposal |
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Report 3 Final Report |
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Source Files |
Source Files |
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Tasks
Week 1 - Complete
A
full literature search of hardware and software security approaches more
specifically in the realm of real-time systems, but because the area is
relatively novel, a much broader search will be employed as well.
Week 2 - Complete
Analyze
simulator and identify components within the simulator that may
exist to aid in
this work. i.e. the Existence of timer interrupts, back-edge
detection
mechanisms.
Weeks 3 and 4 – Mostly Complete
Modify Real-Time Scheduler in
system to support low overhead periodic
checks targeted
solely towards security. Analyze other interrupts that may
occur and analyze the potential
Week 5
Fit Timing Tree’s into scheduler to
enable PC based lookups and
verification
regardless of program input.
Test Against CLAB
Benchmarks
Week 6
Finish collecting
experimental benchmarks
Write
up results into paper for submission
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Mile Stone |
Date Met |
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1 |
3/16/2009 |
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2 |
3/23/2009 |
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3 |
3/31/2009 |
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4 |
4/10/2009 |
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5 |
4/17/2009 |
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6 |
4/21/2009 |
References:
1. "Bounding Worst-Case Instruction Cache Performance" by R. Arnold, F. Mueller, D.
B. Whalley and M. Harmon in IEEE Real-Time Systems Symposium, Dec 1994, pages
172-181 http://moss.csc.ncsu.edu/~mueller/publications.html #19
2. "Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache
Reference Patterns" by H. Ramaprasad and F. Mueller in Real-Time and Embedded
Technology and Applications Symposium, March 2005, pages 148-157.(slides).
http://moss.csc.ncsu.edu/~mueller/ftp/pub/mueller/papers/rtas05dcache.pdf
3. J. Renau, B. Fraguela, J. Tuck, W. Liu, M. Prvulovic, L. Ceze, S. Sarangi, P. Sack, K.
Strauss, and P. Montesinos. SESC Simulator, Jan. 2005, http://sesc.sourceforge.net.