CPU Shielding:
Investigating Real-Time Guarantees Via Resource Partitioning
Scott Tillman
CSC 714 Real-Time Computing Systems
Spring 2009
Objectives
This project seeks to investigate the feasibility and limitations of using CPU shielding to
allow hard real-time operation in commercial, off-the-shelf (COTS) systems. This will be
done by bounding and verifying worst case interrupt response times (CPU contention),
worst case bus reaction times (bus contention), and worst case slowdown associated
with additional cache misses (cache contention). There are existing documents which
discuss various models of these delays. The goal is to verify the models/predictions
and evaluate the predictability that can be achieved using this co-hosting method.
Documents and Timeline
March 16th |
|
Project Proposal |
March 22nd |
|
Replicate system setup from [Brosky]. Evaluate literature predictions of
interference from known sources (PCI, Interrupt and Cache induced) |
March 29th |
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Design/replicate experiments to test latency from known sources |
April 2nd |
|
Initial Project Status Report |
April 5th |
|
Gather and evaluate initial test results. Identify and categorize unknown
latency factors. |
April 19th |
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Demonstrate mixed (real-time and non-real-time) mode operation at
predicted highest frequency |
April 20st |
|
Final Project Summary Slides |
April 21st |
|
Final Project Status Report |
Project Files
Can be found here.
Reference Literature & Links
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Shielded CPUs: real-time performance in standard Linux.
, Steve Brosky. Linux Journal 2004, 121 (May. 2004)
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Realfeel Test of the Preemptible Kernel Patch
, Andrew Webber, Ph.D. Linux Jornal 2002, (October, 2002)
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Toward the Predictable Integration of Real-Time COTS Based Systems
, Marco Caccamo.
Slides from 28 October, 2008
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Coscheduling of CPU and I/O Transactions in COTS-based Embedded Systems
, Rodolfo Pellizzoni, Bach Bui, Marco Caccamo, Lui Sha. Real-Time Systems Symposium, 2008
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Allowing cycle-stealing direct memory access I/O concurrent with hard-real-time programs.
, Tai-Yi Huang, Jane W.-S. Lui, Jen-Yao Chung. International Conference on Parallel and Distributed Systems, Tokyo, 1996
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Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture
, Dhruba Chandra, Fei Guo, Seongbeom Kim, and Yan Solihin. Proceedings of the 11th Int’l Symposium on High-Performance Computer Architecture
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Impact of PCI-bus load on applications in a PC architecture
, Sebastian Schönberg, Proceedings of the 24th IEEE international Real-Time Systems Symposium,
Cancun, Mexico, December 2003
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PCI Local Bus Specification, Revision 2.2
, PCI Special Intrest Group, December 18, 1998
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AMD Atlon 64 Processor Product Data Sheet, Revision 3.18
, Advanced Micro Devices, Publication #24659, September 2006
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The Worst-Case Execution Time Problem - Overview of Methods and Survey of Tools
, R. Wilhelm, J. Engblohm, A. Ermedahl, N. Holsti, S. Thesing, D. Whalley, G.
Bernat, C. Ferdinand, R. Heckmann, T. Mitra, F. Mueller, I. Puaut, P. Puschner, J. Staschulat, P. Stenström,
ACM Transactions on Embedded Computing Systems, Vol. 7, No. 3, Apr 2008, pages 1-53