Project statement
We intend to design and simulate a
power-aware real time scheduling scheme. The scheduling schemes discussed so
far in class ensure timely completion of jobs but they are oblivious to power
consumption. Today with the advent of small-sized computing systems and SoCs, power management is of high importance. In this work
we intend to make the existing scheduling schemes power-aware so that we can
minimize power consumption while meeting the deadlines.
Documents
Milestones
Ø Week 1 : Complete the literature survey and
study about existing work(Neha and Xiaoqing) Done
Ø Week 2 : Build vanilla scheduler simulator
(Neha) Done
Come up with task sets that would be fed into the
simulator and perform static timing analysis Done
considering all the possible dvfs
frequencies (Xiaoqing) Done
Ø Week 3 : Design and implement acceptance
test for aperiodic jobs in the simulator (Neha) Done
Design
and implement the reaction mechanism in the simulator (Xiaoqing)
Done
Ø Week 4: Run the tasks sets developed by Xiaoqing on the simualtor and
interpret the results (Xiaoqing, Neha)
Done
Ø Week 5 : Debugging and further
experimentation (Xiaoqing, Neha) Done
Ø Week 6 : Presentation and final report
submission (Xiaoqing, Neha) Done
Source Code
References
l DVSleak: Combining Leakage Reduction and Voltage
Scaling in Feedback EDF Scheduling (http://moss.csc.ncsu.edu/~mueller/ftp/pub/mueller/papers/lctes07.pdf)
l Real-Time Dynamic Voltage Scaling for
Low-Power Embedded Operating Systems, P. Pillai and K. Shin, Symposium on
Operating Systems Principles'01
l Effective Dynamic VoltageScaling
through CPU-Boundedness Detection, C.-H. Hsu and
W.-C. Feng, in Proceedings of the 4th International Conference on Power-Aware
Computer Systems, ser. PACS’04, 2005
l Memory Access Aware on-line Voltage Control
for Performance and Energy Optimization, X. Chen, C. Xu, and R. Dick, in
Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on, 2010,
pp.365–372.