Memory access latency prediction in shared multiple memory controllers

Xing Pan (xpan@ncsu.edu)

Our goal is to design a new coloring allocation algorithm based on memory controller to help us to predict the memory access latency exactly.

Introduction:

In safety-critical cyber-physical systems, the usage of multicore platforms has been hampered by problems due to interactions across cores through shared hardware. Shared resource access interference, particularly memory and system bus, is a big challenge in designing predictable real-time systems because its worst case behavior can significantly differ. In this project, I will get a study on the shared multiple memory controllers latency and propose a new virtual and physical address mapping algorithm help us to predict the memory access latency exactly.

Document:

Proposal

Report2

Report3

Final report

Configuration steps:

Step1. Utilize brute-force test program to verify the shared multiple memory access latency existed. by 3/24/2014 

Step2. Configure out the AMD Opteron 6128 architecture. by 4/11/2014 

Step3. Test the contend and latency between multiple threads in multicore system. by 4/21/2014

Step4. Coloring algorithm design and Evaluation. by 5/1/2014

Conclusion

Due there are several memory controllers in the modern CPU, the memory accessing latency is very hard to predict and the WECT is also not exactly in real time system. This project proposes a new coloring allocation algorithm to solve the memory accessing latency prediction problem in modern CPU. For the modern CPU, the new coloring allocation algorithm color main memory based on the memory controller. Each task in real time system will be assigned the different colored memory bank. As the result, we also show the correctness and latency predictable of this algorithm. So we can apply modern CPU (multiple memory controllers) in real time system by using the coloring allocation. Additionally, using the color allocation could also get better performance of memory accessing latency than general allocation.

Opening problem

        1. Modify the algorithm and the kernel in the Linux. We still need to modify the allocation to make the tasks could access the remote memory controller. 

        2. Try to find whether there is any other reason for the latency

        3. Try to realize dynamic coloring memory allocation.

        4. Consider the memory fragment problem when we assign the colored memory bank to task.

        5. Now, the coloring allocation only supports at most 4 tasks. We need to modify it to support more tasks.

References:

[1] TILEPROCESSOR ARCHITECTURE OVERVIEW FOR THE TILEPROSERIES
[2] Christopher Zimmer and Frank Mueller. Low Contention Mapping of Real-Time Tasks onto a TilePro 64 Core Processor.
[3] Balasubramanya Bhat and Frank Mueller. Making DRAM Refresh Predictable
[4] Zheng Pei Wu, Yogen Krish, and Rodolfo Pellizzoni. Worst Case Analysis of DRAM Latency in Multi-Requestor Systems
[5] Heechul Yun, Gang Yao, Rodolfo Pellizzoni, Marco Caccamo and Lui Sha. Memory Access Control in Multiprocessor for Real-time Systems with Mixed Criticality
[6] Wei Wang, Tanima Dey, Jack W. Davidson, and Mary Lou Soffa. DraMon: Predicting Memory Bandwidth Usage of Multi-threaded Programs with High Accuracy and Low Overhead
[7] Noriaki Suzuki, Hyoseung Kim, Dionisio de Niz. Coordinated Bank and Cache Coloring for Temporal Protection of Memory Accesses
[8] Hyoseung Kim, Dionisio de Niz, Bjorn Andersson. Bounding Memory Interference Delay in COTS-based Multi-Core Systems.
[9] Heechul Yun, Renato Mancuso, Zheng-Pei Wu, Rodolfo Pellizzoni . PALLOC: DRAM Bank-Aware Memory Allocator for Performance Isolation on Multicore Platforms,