Low-end embedded architectures, such as sensor nodes, have become popular in 
diverse fields, many of which impose real-time constraints. Currently, the 
Atmel Atmega processor family used by Berkeley Motes lacks support for 
deriving safe bounds on the WCET, which is a prerequisite for performing 
real-time schedulability analysis. Our work fills this gap by providing an 
analytical method to obtain WCET bounds for this processor architecture.

Our first contribution is to analyze both C and NesC code, the latter of 
which is unprecedented. The second contribution is to model control hazards 
and variable-cycle instructions, both handled more efficiently by our approach
 than by previous ones and results in up to 77\% improvement in bounding the 
WCET. The results demonstrate that our timing analysis framework is able to 
tightly and safely estimate the WCET of the benchmarks while simulator results
 are shown to not always provide safe WCET bounds. While motivated by the 
Atmel Atmega series of processors, results are equally applicable to low-end 
embedded processors.

This work is, to the best of our knowledge, the first set of experiments 
where timing results are contrasted from execution on an actual processor, 
from a cycle-accurate simulator and from a static timing analyzer. Furthermore,
 making our timing analysis toolset available to the Atmel Atmega processor 
family is a significant contribution towards addressing a documented need for 
tool support for sensor node architectures commonly used in networked systems 
of embedded computers, or so-called EmNets.