Title: "CheckerMode : A hybrid scheme for timing analysis of modern processor pipelines involving hardware/software interactions

Abstract:
　

Real-time systems often require determinism to ensure
that task deadlines are met. Schedulability analysis provides
a firm basis to ensure that tasks deadlines are met, and for
this, knowledge of bounds on worst-case execution times
(WCET) of tasks is a critical piece of information. Static timing
analysis derives these bounds on WCETs. A limiting factor
for real-time systems design is the class of processors
that may be used. Contemporary processors with their advanced
architectural features, such as out-of-order execution,
branch prediction, speculation, and prefetching, cannot
be statically analyzed to obtainWCETs for tasks because
these features introduce non-determinism to task execution,
which can only be resolved at run-time. We introduce a new
paradigm which proposes minor enhancements to modern
processor architectures, which, on interaction with software
modules, is able to obtain tight, accurate timing analysis results
for modern processors. To the best of our knowledge,
this method of hardware/software interactions to calculate
WCET results for out-of-order processors is the first of its
kind.