MAESTRO: A Many-Core Runtime for Power Managements

Presenter: Allan Porterfield

Bio

Rice University, Electrical Engineering, BSEE, 1981.
Rice University, Computer Science, M.S., 1988.
Rice University, Computer Science, Ph.D., 1989. (adviser Ken Kennedy)

I spent 17 years at Tera (become Cray Inc) as part of a small group (2-5) responsible for design and implementation of all language related tools including a highly optimizing parallel compiler, runtime libraries, incremental linker, debugger, performance tools, and instruction set simulator. I have been at RENCI for 15 months and have joined the performance tools projects looking at ways to increase application performance on large systems. I'm PI of the MAESTRO project funded by the DoD, looking into runtime designs that conserve power without effecting performance.

Abstract

Core counts will increase in the next several years to tens of cores per processor. Memory bandwidth will increase but only for blocks of data. Applications will find supplying the parallelism required by the cores while generating the locality required by the processor difficult. Applications will not be able to profitably use all of the cores on the processor. MAESTRO will use the excess computational resources, to monitor execution at a level previously considered too intrusive. Early results are promising. A daemon that controls processor frequency to limit power when an AMD Phenom L3 cache is busy, greatly reduces power consumption for minor performance penalty on some benchmarks.