Instructions on how to use Timing Analysis Framework
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Index

1) Tools List
2) Installation
3) pcompiler : details
4) staticsim : details
5) timing analyser : details
6) Using the "timing_script" to simplify the process

1) Tools List

The following tools are provided as a part of this timing analysis framework:
	 * pcompiler : creates the "inf" and "path" files for use by other tools.
	 * staticsim : creates the "ist" file for use by the timing analyser.
	 * timing analyser : uses the "inf" and "ist" files for calculation of WCET.
	 * timing_script : provides a convenient method for usage of above tools.


2) Installation

Untar the timing_analyser.tar archive into required directory.


3) pcompiler : details

The pcompiler requires the following files:
* the assembly file for which WCET bounds are to be obtained : my_file.s
* a loop file which provides details of all the loops and functions in the program. "loop_file_template.txt" provides details on how this file must be created.
  As of now, this file must be created by hand.
  Please Note : The order of the loops and functions in the loop file, MUST be in the same order of appearance as in the assembly file.

Now, to execute the pcompiler, follow these steps:
* Copy the assembly and loop files to the folder with the pcompiler
* pcompiler <assembly file> <output file>

The <output_file> is of the same name as the assembly file, but without the .s extension

The outputs are :
- inf file	- for the timing analyser
- path file	- for staticsim

Copy the .path file to the folder with the staticsim.
Copy the inf file to the timing analyser directory


4) staticsim : details

The staticsim is the static cache simulator. It requires the following files :
* path file from the pcompiler
* trace.config file : for information on the cache.

The trace.config file template is provided in the trace.config.atmel file in the staticsim folder.
Please Note : BOTH the timing analyser and staticsim require the same trace.config file.

All the fields of the trace.config file are self-explanatory. The number of entries in the "Miss Delay" line, may vary, depending on the Cache configruation
provided. Let n = Line Size / Set Size. Repeat the miss delay value "n" times.

To execute the staticsim, follow these steps:
* Copy the .path file to the folder with the staticsim
* staticsim -t <file> 				/* Note : file = path file... don't give extension. */
* epilogue < "file.ist"  > temp.ist		/* This is a tool in the staticsim directory to truncate the ist file. */
* mv temp.ist to mod_timing/file.ist		/* This is the file that the Timing Analyser uses. */


5) timing analyser : details

The timing analyser is in the folder mod_timing and the executable is called "time.bin"

It requires the following input files:
* inf file from pcompiler.
* ist file from staticsim - rather the output of the epilogue program.
* trace.config file

To obtain the wcet information:
* time.bin <file>		/* Note : no extension required */

The outputs are :
- WCET information for each loop and function provided in the loop file.
- WCET information for the entire program.


** Note : All of the above steps are explained in the file : timing_steps.txt **


6) Using the "timing_script" to simplify the process

All steps explained above( i.e. in the timing_steps.txt file ) need to be performed manually for each assembly file. 

To simplify the process, a script is provided, which, if a few environment variables are set, will execute each tool in turn, and obtain the WCET for a given assemble file.

The following environment variables are required:
* TIMING_FILE
* TIMING_CACHE_SIZE
* TIMING_OUTPUT_DIRECTORY

Further explanations for use of these environment variables is provided in the comments section of the script itself.

The outputs will be in the folder that was provided by the TIMING_OUTPUT_DIRECTORY variable.