PowerPC instructions

Whenever instruction addresses are presented to the processor, the low-order 2 bits are ignored.

Similarly, whenever the processor develops an instruction address, the low-order 2 bits are zero. The address of either an instruction or a multiple-byte data value is its lowest-numbered byte. This address points to the most-significant end (big-endian convention). The little-endian convention is not supported.

Arithmetic for address computation is unsigned and ignores any carry out of bit 0 (the MSb).

For an overview of the big-endian bit and byte numbering used by the PPE, see Byte ordering and bit numbering.

• Addressing modes
  All instructions, except branches, generate addresses by incrementing a program counter. All load and store instructions specify a base register.
• Instruction types
  The PowerPC Processor Element (PPE)'s PowerPC instructions can have up to three operands. Most computational instructions specify two source operands and one destination operand.
• Compatibility with existing PowerPC code
  The PowerPC Processor Element (PPE) complies with version 2.0.2 of the PowerPC architecture, with only minor exceptions.