PowerT: Reducing Frequency via Speculation and Fall-Back Recovery

This work puts forth a two-tier approach to reduce the processor frequency of complex embedded systems. First, tight worst-case timing analysis reduces the perceived upper bound on the number of cycles consumed by tasks. This reduces the maximum frequency, saving power. Second, architecture simulation and processors with dual frequency/voltage modes enable significant additional power savings. Architecture simulation produces an approximate worst-case timing estimate, which does not have to be safe and, consequently, is the basis for a very low speculative frequency. A higher recovery frequency is utilized as a fall-back mode to ensure safe operation bounded by tight worst-case timing analysis, as delivered in the first approach. These two approaches complement each other. They initially reduce the power requirements by a significant amount when compared with the naive approach. Additionally, they reduce power requirements further by exploiting simulation to accurately speculate the clock frequency.

Code distributions:
"This material is based upon work supported by the National Science Foundation under Grant No. 0208581."

"Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation."