PowerT: Reducing Frequency via Speculation and Fall-Back Recovery

• funded by: NSF (award abstract)
• funding level: $300,000
• duration: 07/01/2002 - 06/30/2005 (no-cost extension till 06/30/2006)
• PIs: Frank Mueller, Eric Rotenberg

This work puts forth a two-tier approach to reduce the processor frequency of complex embedded systems. First, tight worst-case timing analysis reduces the perceived upper bound on the number of cycles consumed by tasks. This reduces the maximum frequency, saving power. Second, architecture simulation and processors with dual frequency/voltage modes enable significant additional power savings. Architecture simulation produces an approximate worst-case timing estimate, which does not have to be safe and, consequently, is the basis for a very low speculative frequency. A higher recovery frequency is utilized as a fall-back mode to ensure safe operation bounded by tight worst-case timing analysis, as delivered in the first approach. These two approaches complement each other. They initially reduce the power requirements by a significant amount when compared with the naive approach. Additionally, they reduce power requirements further by exploiting simulation to accurately speculate the clock frequency.

• We promote customized embedded architectures for power consumption.
  • A frequency-aware approach to timing analysis using parametric abstraction is described in FAST: Frequency-Aware Static Timing Analysis.

• We are investigating real-time operating system support for power-aware systems.
  • A Feedback DVS model for EDF makes earliest-deadline first scheduling for hard real-time systems energy conserving by splitting tasks and utilizing feedback on execution requirements. The method results in up to 34% reduction in energy consumption over the best previously published methods.

  • A detailed account of Preemption Handling is given in a separate publication that discussed different slack and idle reclaimation schemes.

  • A feedback EDF scheduling technique that reduces power even more effectively than previous techniques is described in Feedback EDF Scheduling Exploiting Dynamic Voltage Scaling (DVS), which was later extended by a proof and experiments in a journal version.

  • We also implemented our Feedback EDF-DVS Scheduling on the PowerPC 405LP and compared results with the best known algorithms in the field. Our approach compares favorably: It has the lowest energy consumption, even through the scheduling decisions inflict slightly more overhead. This overhead is accounted for in the power measurements. An extended journal version further compares a combined (single) feedback technique with separate feedbacks for each task.
  • The apprach was extended to combine DVS techniques with sleep modes to reduce both dynamic and static power taking into account the trade-offs due to critical speed and wakeup overheads.

• "Frequency-aware Static Timing Analysis for Power-aware Embedded Architectures" by Kiran Seth, M.S., North Carolina State University, Dec 2003 (last known position: QualComm, NC)
• "Dynamic Voltage Scaling with Feedback EDF Scheduling for Real-Time Embedded Systems" by Y. Zhu, Ph.D. Thesis, North Carolina State University, Aug 2005 (last known position: Sony-Ericsson, NC)

• A Feedback EDF-DVS Real-Time Scheduling Simulator

"Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation."