References

  • Intel 64 and IA-32 Architecture’s software development mannual, Volume 1 http://download.intel.com/products/processor/manual/253665.pdf
  • Intel 64 and IA-32 Architecture’s software development mannual, Volume 3A http://download.intel.com/products/processor/manual/253668.pdf
  • Intel 64 and IA-32 Architecture’s software development mannual, Volume 3B http://download.intel.com/products/processor/manual/253669.pdfs
  • Accurate TLB and cache characterization using hardware counters http://web.eecs.utk.edu/ shirley/papers/iccs04.pdf
  • PAPI Library - http://icl.cs.utk.edu/papi/
  • http://www.seco.com/
  • http://www.litmus-rt.org/
  • Technical reference manual Tegra3
  • AMBA Level2CacheController (L2C-310) Revision: r3p1 Technical Reference Manual
  • Making Shared Caches More Predictable on Multicore Platforms Bryan C. Ward, Jonathan L. Herman, Christopher J. Kenna, and James H. Anderson, Department of Computer Science, University of North Carolina at Chapel Hill
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