| Name | Task | Due date | Status | | Yasaswini | Porting cache coloring on Tegra3 |
| |
| 1.Install PAPI library
| 3/19/2014 | Done |
| 2.Patch-up Linux kernel with colored-malloc implementation of LitmusRT | 3/25/2014 | Done |
| 3.Study changes required for Tegra3 cache coloring, identify and resolve implementation issues during booting of kernel | 4/08/2014 | Done |
| 4.Run Litmus-RT patched kernel, liblitmus based applications | 4/12/2014 | Done |
| 5.Run experiments and collect the results | 4/20/2014 | Done |
|
|
| | | Shrinivas | Implementing TLB coloring on Tegra3 |
| |
| 1.Find virtual address to DTLB mapping for tegra 3 | 3/19/2014 | Done |
| 2.Design experiment which maps 3 pages to L2 DTLB ( 2 way set associative) - 3 pages are accessed in cyclic manner | 3/30/2014 | Done | | | 3. Find out how the L2 DTLB can be configured to support 128 entries. (take away the lockable entries)
| 4/5/2014
| Done |
| 4.Change tlb_malloc code to allocate for Tegra 3 - since there would be a change in the way mappings are done, there would be code changes required | 4/09/2014 | Done |
| 5.Design experiment to show worst case and best case for tlb coloring - similar to the one designed for Intel | 4/15/2014 | Done |
| 6.Run experiments and collect results | 4/21/2014 | Done |
|
|
| | | Payal | Integration of TLB coloring and cache coloring |
| |
| 1.Study the functionalities and working of TLB coloring code in depth | 3/20/2014 | Done |
| 2.Study the functionalities and working of Cache coloring code in depth | 3/24/2014 | Done |
| 3.Running experiments of tlb_malloc and color_malloc module | 3/26/2014 | Done |
| 4.Integration of TLB coloring and Cache coloring | 4/12/2014 | Done |
| 5.Design test cases | 4/18/2014 | Done |
| 6.Integration testing of tlb coloring with cache coloring | 4/23/2014 | Done |
| 7.Run experiments ,collect and analyse the results | 4/26/2014 | |
|
|
