Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems

This project resolves a long-standing problem in embedded systems: bounding the worst-case execution times (WCET) of tasks on contemporary processors. WCETs are essential for real-time scheduling; yet deriving them for contemporary processors is intractable. The Virtual Simple Architecture (VISA) framework shifts the burden of bounding the WCETs of tasks, in part, to hardware. A VISA is the pipeline timing specification of a hypothetical simple processor. WCET is derived for a task assuming the VISA. At run-time, the task is executed speculatively on an unsafe complex processor, and its progress is continuously gauged. If continued safe progress appears to be in jeopardy, the complex processor is reconfigured to a simple mode of operation that directly implements the VISA, thereby explicitly bounding the task's overall execution time by the WCET.

VISA provides a general framework for safe operation on unsafe processors, setting up new opportunities for exploiting higher performance in embedded systems.

The project aimes at contributing to a shift in computing to support an evolving demand for predictability in embedded computers with real-time constraints (e.g., cell phones, cars, airplanes, appliances, industry/military applications, etc.). This project radically increases the performance, functionality, and reliability of embedded systems, which are vital to the day-to-day functioning of our society.

"This material is based upon work supported by the National Science Foundation under Grant No. 0310860."

"Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation."