The Cell Broadband Engine consists
of nine processors on a single chip, all connected to each other and
to external devices by a high-bandwidth, memory-coherent bus.
shows a block diagram of the Cell Broadband Engine
. The main blocks include the:
- PowerPC Processor Element (PPE). The PPE is the main processor.
It contains a 64-bit PowerPC Architecture reduced instruction set computer
(RISC) core with a traditional virtual-memory subsystem. It runs an operating
system, manages system resources, and is intended primarily for control processing,
including the allocation and management of SPE threads. It can run legacy
PowerPC Architecture software and performs well executing system-control code.
It supports both the PowerPC instruction set and the Vector/SIMD Multimedia
Extension instruction set.
- Synergistic Processor Elements (SPEs). The eight SPEs are SIMD
processors optimized for data-rich operations allocated to them by the PPE.
Each of these identical elements contains a RISC core, 256-KB, software-controlled
local store for instructions and data, and a large (128-bit, 128-entry) unified
register file. The SPEs support a special SIMD instruction set, and they rely
on asynchronous DMA transfers to move data and instructions between main storage
(the effective-address space that includes main memory) and their local stores.
SPE DMA transfers access main storage using PowerPC effective addresses. As
on the PPE, address translation is governed by PowerPC Architecture segment
and page tables. The SPEs are not intended to run an operating system.
- Element Interconnect Bus (EIB). The PPE and SPEs communicate coherently
with each other and with main storage and I/O through the EIB. The EIB is
a 4-ring structure (two clockwise and two counterclockwise) for data, and
a tree structure for commands. The EIB’s internal bandwidth is 96 bytes per
cycle, and it can support more than 100 outstanding DMA memory requests between
main storage and the SPEs.
Figure 1. Overview
of Cell Broadband Engine architecture
The memory-coherent EIB has two
external interfaces, as shown in Figure 1
- The Memory Interface Controller (MIC) provides the interface between
the EIB and main storage. It supports two Rambus Extreme Data Rate (XDR) I/O
(XIO) memory channels and memory accesses on each channel of 1-8, 16, 32,
64, or 128 bytes.
- The Cell Broadband Engine Interface (BEI) manages data transfers
between the EIB and I/O devices. It provides address translation, command
processing, an internal interrupt controller, and bus interfacing. It supports
two Rambus FlexIO external I/O channels. One channel supports only non-coherent
I/O devices. The other channel can be configured to support either non-coherent
transfers or coherent transfers that extend the logical EIB to another compatible
external device, such as another Cell Broadband Engine.
The Cell Broadband Engine supports concurrent
real-time and non-real-time operating systems and resource management. Software
development in the C/C++ language is supported by a rich set of language extensions
that define C/C++ data types for SIMD operations and map C/C++ intrinsics
(commands, in the form of function calls) to one or more assembly instructions.
These language extensions give C/C++ programmers much greater control over
code performance, without the need for assembly-language programming. Software
development is further supported by:
- a complete Linux-based SDK,
- a full-system simulator, and
- a rich set of application libraries, performance tools and debug tools.
- The PowerPC Processor Element
The PowerPC Processor Element (PPE) is a general-purpose, dual-threaded, 64-bit RISC processor that conforms to the PowerPC Architecture, version 2.02, with the Vector/SIMD Multimedia Extension.
- Synergistic Processor Elements
Each of the eight Synergistic Processor Elements (SPEs) is a 128-bit RISC processor specialized for data-rich, compute-intensive SIMD applications.