Channels

Channels are unidirectional message-passing interfaces that support 32-bit messages and commands. Many of the channels provide communications between the SPE and its MFC, which in turn, mediates communication with the PPE and other devices.

Table 1 lists the channels and their attributes. Reserved and privileged channels are omitted.

Software on the SPU uses special channel instructions (shown in Table 1) to read and write channel registers and queues.

Software on the PPE and other devices use load and store instructions to read and write to MFC's MMIO registers that are associated with the SPU's channels.

Table 1. SPE Channels
Channel Name Mnemonic Size (bits) R/W Blocking
SPU Events
0 SPU Read Event Status SPU_RdEventStat 32 R Yes
1 SPU Write Event Mask SPU_WrEventMask 32 W No
2 SPU Write Event Acknowledgment SPU_WrEventAck 32 W No
SPU Signal Notification
3 SPU Signal Notification 1 SPU_RdSigNotify1 32 R Yes
4 SPU Signal Notification 2 SPU_RdSigNotify2 32 R Yes
SPU Decrementer
7 SPU Write Decrementer SPU_WrDec 32 W No
8 SPU Read Decrementer SPU_RdDec 32 R No
MFC Multisource Synchronization
9 MFC Write Multisource Synchronization Request MFC_WrMSSyncReq 32 W Yes
SPU and MFC Read Mask
11 SPU Read Event Mask SPU_RdEventMask 32 R No
12 MFC Read Tag-Group Query Mask MFC_RdTagMask 32 R No
SPU State Management
13 SPU Read Machine Status SPU_RdMachStat 32 R No
14 SPU Write State Save-and-Restore SPU_WrSRR0 32 W No
15 SPU Read State Save-and-Restore SPU_RdSRR0 32 R No
MFC Command Parameters
16 MFC Local Store Address MFC_LSA 32 W No
17 MFC Effective Address High MFC_EAH 32 W No
18 MFC Effective Address Low or List Address MFC_EAL 32 W No
19 MFC Transfer Size or List Size MFC_Size 16 W No
20 MFC Command Tag Identification MFC_TagID 16 W No
21 MFC Command Opcode or ClassID MFC_Cmd 32 W Yes
MFC Tag Status
22 MFC Write Tag-Group Query Mask MFC_WrTagMask 32 W No
23 MFC Write Tag Status Update Request MFC_WrTagUpdate 32 W Yes
24 MFC Read Tag-Group Status MFC_RdTagStat 32 R Yes
25 MFC Read List Stall-and-Notify Tag Status MFC_RdListStallStat 32 R Yes
26 MFC Write List Stall-and-Notify Tag Acknowledgement MFC_WrListStallAck 32 W No
27 MFC Read Atomic Command Status MFC_RdAtomicStat 32 R Yes
SPU Mailboxes
28 SPU Write Outbound Mailbox SPU_WrOutMbox 32 W Yes
29 SPU Read Inbound Mailbox SPU_RdInMbox 32 R Yes
30 SPU Write Outbound Interrupt Mailbox SPU_WrOutIntrMbox 32 W Yes

Each channel has a corresponding count that indicates the remaining capacity (the maximum number of outstanding transfers) in that channel. This count is decremented when a channel instruction is issued to the channel, and the count increments when an action associated with that channel completes. Each channel is implemented with either blocking or non-blocking semantics.

Blocking channels cause the SPE to stall (suspend execution in a low-power state) when the SPE reads or writes a channel with a count of zero.

Key features of the SPE channel operations include:

  1. Channel instructions
    The SPU Instruction Set Architecture defines three channel instructions: rdch, wrch, and rchcnt.
  2. Mailboxes
    Mailboxes are queues that support exchanges of 32-bit messages between an SPE and other devices. Each mailbox queue has an SPE channel assignment as well as a corresponding MMIO register assignment.
  3. Signal notification
    Signal-notification channels, or signals , are inbound (to an SPE) registers. They can be used by other SPEs, the PPE, or other devices to send information, such as a buffer-completion synchronization flag, to an SPE.
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