SPE configuration

This section describes the main components of a Synergistic Processor Element (SPE).

The main components are shown in Figure 1. Their functions include:

• Synergistic Processor Unit (SPU) — The SPU executes SPU instructions fetched from its 256-KB LS. The SPU fills its LS with instructions and data using DMA transfers initiated from SPU or PPE software.
• Memory Flow Controller (MFC) — The MFC provides the interface, by means of the Element Interconnect bus (EIB), between the SPU and main storage. The MFC performs DMA transfers between the SPU's LS and main storage, and it supports mailbox and signal-notification messaging between the SPE and the PPE and other devices. The SPU communicates with its MFC through SPU channels. The PPE and other devices (including other SPEs) communicate with an MFC through memory-mapped I/O (MMIO) registers associated with the SPU's channels.

1. Synergistic Processor Unit
   Each of the eight SPEs is an independent processor with its own program counter, register file, and 256-KB LS.
2. Memory flow controller
   The primary functions of the Memory Flow Controller (MFC) are to connect the SPU to the EIB and support DMA transfers between main storage and the LS.
3. Channels
   Channels are unidirectional message-passing interfaces that support 32-bit messages and commands. Many of the channels provide communications between the SPE and its MFC, which in turn, mediates communication with the PPE and other devices.