SPU instruction set

The SPU Instruction Set Architecture (ISA) fully documents the instructions supported by the SPEs. This section summarizes the ISA.

Programmers writing in a high-level language like C or C++ can use the intrinsics described in SPU C/C++ language extensions (intrinsics) to improve their control over the SPE hardware. Because the functions performed by these intrinsics are closely related to the assembly-language instructions of the SPU Instruction Set Architecture , this overview may be helpful in understanding the utility of the intrinsics.

The SPU ISA operates primarily on SIMD vector operands, both fixed-point and floating-point, with support for some scalar operands. The PPE and the SPE both execute SIMD instructions, but the two processors execute different instruction sets, and programs for the PPE and SPEs must be compiled by different compilers.

1. Data layout in registers
   The SPE supports big-endian data ordering, an ordering in which the lowest-address byte and lowest-numbered bit are the most-significant (high) byte and bit, respectively.
2. Instruction types
   There are 204 instructions in the SPU Instruction Set Architecture , and they are grouped into 11 classes according to their functionality.