Channel instructions

The SPU Instruction Set Architecture defines three channel instructions: rdch, wrch, and rchcnt.

A summary of the SPU Instruction Set Architecture is shown in SPU instruction set. The rdch, wrch, and rchcnt channel instructions are shown in Table 1.

Software running on an SPE uses the channel instructions to write parameters and enqueue the MFC commands, as described in MFC commands.

Table 1 includes both the SPU assembly-language instructions and their corresponding C-language intrinsics.

The intrinsics are described in SPU C/C++ language extensions (intrinsics).

Table 1. SPE Channel Instructions
Instruction	Assembler Instruction	C-Language Intrinsic	Description
Read Channel	rdch	spu_readch spu_readchqw	Causes data to be read from the addressed channel and stored into the selected General-Purpose Register (GPR).
Write Channel	wrch	spu_writech spu_writechqw	Causes data to be read from the selected GPR and stored in the addressed channel
Read Channel Count	rchcnt	spu_readchcnt	Causes the count associated with the addressed channel to be stored in the selected GPR.

If the write channel is nonblocking, a wrch instruction can be issued regardless of the value of the channel count for that channel. If the write channel is blocking , then a wrch instruction that is issued when the count for that channel is equal to zero will stall the SPE. Stalling on a wrch instruction can be useful because it saves power, but to avoid stalling, software should first read the channel count to ensure that it is not zero before issuing a wrch instruction.

The method used to determine the channel count is dependent on the program. The program can poll the channel count for that register, using the rchcnt instruction, or the program can issue a wrch instruction. If the program issues a wrch instruction, the SPE stalls, waiting until an acknowledgment is received from the write channel.

When an SPE program needs to receive information, it uses a rdch instruction. Usually, this information is held in an SPE register. The information can be loaded into this register through the channel interface using a read-data-load transaction.

If the read channel is nonblocking, then a rdch instruction can be issued regardless of the value of the channel count for that channel.
In the SPE, if the channel is a blocking channel, the SPE does not read from this register until the channel count for that register indicates that the data is valid (that is, when the count is greater than zero).
If the count is zero, then there is no data in the channel and the SPE stalls until actions associated with that channel occur.

These actions can include the updating of the MFC_RdTagStat channel (see Table 1), the PPE writing data to the corresponding MMIO register (such as a mailbox channel), or other actions. The method used to determine the count depends on the program. The program can:

poll the channel count for that register using the rchcnt instruction, or
issue the rdch instruction.

If the program issues a rdch instruction, the SPE stalls, waiting until valid data is loaded.

The channel instructions are architected as 128 bits wide, but in the Cell Broadband Engine, channel instructions set use only the 32 bits from the preferred slot (the left-most word, word element 0) in the register.