Checker: CSR--EHS: Collaborative Research: Hybrid Timing Analysis via Multi-Mode Execution

Current software design for safety-critical embedded systems requires stringent compliance with coding standards to ensure safety and reliability. A key additional requirement for real-time embedded systems is predictable timing behavior of software components, which requires that bounds on the worst-case execution time (WCET) of embedded software be determined.
While static timing analysis yields verifiable bounds on the WCET, it cannot keep pace with architectural innovations and hardware performance variation due to chip fabrication scaling.

This work contributes a fundamentally new approach to bounding the WCET with three major contributions:
1. Instead of simulating execution, actual execution in hardware is promoted to assess a task's WCET. This approach not only renders tedious hardware modeling unnecessary but also guarantees correct behavior regardless of architectural complexity or hardware variation.
2. The approach will be evaluated and its complexity by FPGA synthesis. This assesses the feasibility of the design and validates a prototype implementation.
3. The impact of advanced architectural features is studied in co-design space exploration to providing predictability and tight WCET bounds.

The proposed research advances existing science and technology through novel techniques in hardware and software design for safety-critical embedded real-time systems by
1) providing high-confidence bounds on execution times;
2) enhancing hardware architectures with support to assess execution times; and
3) customizing hardware features via co-design to improve predictability.

Publications: Theses:
"This material is based upon work supported by the National Science Foundation under Grant No. 0720496."

"Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation."