Index

• __builtin_expect
• _align_hint directive

• ABI (Application Binary Interface) (1), (2)
• Accelerated Library Framework
• addressing modes (1), (2)
• aligned attribute
• AOS (array of structures) (1), (2)
• Application Binary Interface (ABI) (1), (2)
• architecture of the PPE
• array of structures (AOS) (1), (2)
• array-summing example
• asymmetric-thread runtime model
• auto-vectorizing compiler

• barrier commands
• barriers and fences
• basic blocks
• BHT (branch history table)
• big-endian byte and bit ordering
• big-endian ordering
• blocking channel
• branch hints (1), (2)
• branch history table (BHT)
• branch mispredicts
• branch target instruction cache (BTIC)
• BTIC (branch target instruction cache)
• built-Ins
• byte ordering

• C/C++ language extensions
• CBEA (Cell Broadband Engine Architecture)
• Cell Application Frameworks
• Cell Broadband Engine Architecture (CBEA) (1), (2), (3)
• Cell Broadband Engine Architecture, overview
• Cell Broadband Engine Linux task
• Cell Broadband Engine program, performance optimization
• channel domains
• checkpoints
• clamping
• command-line interface
• command-line mode
• commands, DMA
• commands, synchronization
• compatibility with existing PowerPC code
• compiler directives
• composite intrinsics
• computation-acceleration model
• condition register (CR)
• console window
• control plane (1), (2)
• count register (CTR)
• CR (condition register)
• CTR (count register)
• cycle-accurate simulation (1), (2)

• data plane (1), (2), (3)
• data types
• debugging
• decrementer (timer)
• denormals
• dependencies
• device-extension model
• Direct Memory Access Controller (DMAC)
• directives
• directory structure
• DMA command, tag groups
• DMA commands (1), (2)
• DMA commands, get
• DMA commands, put
• DMA list, creating
• DMA-list transfers
• DMA-list transfers, programming example
• DMA transfers (1), (2), (3), (4)
• DMAC (Direct Memory Access Controller)
• double buffering
• double buffering (programming example)
• dual-issue
• dynamic branch prediction
• dynamic timing analysis
• dynamic timing analysis, on the IBM Full System Simulator

• EA (effective address) (1), (2), (3), (4), (5), (6)
• ECC (error-correcting code)
• Eclipse IDE
• effective address (EA) (1), (2), (3), (4), (5), (6)
• Effective-to-Real Address Translation
• Element Interconnect Bus (EIB) (1), (2)
• emitters
• error-correcting code (ECC)
• Euler, particle-system simulation
• example, array-summing
• example, using Vector instructions in PPE program
• example program, tpa1
• executables

• fast mode
• fenced command option
• fetch group
• fixed-point exception register (XER)
• floating-point registers (FPRs)
• floating-point status and control register (FPSCR)
• Floating-Point Status and Control Register (FPSCR)
• FPRegs
• FPRs (floating-point registers)
• FPSCR (floating-point status and control register)
• FPSCR (Floating-Point Status and Control Register)
• fscrrd instruction
• fscrwr instruction
• Full System Simulator, for the Cell Broadband Engine
• function-inlining
• function offload model
• functional simulation
• functions, running on the SPEs

• general-purpose registers (GPRs)
• General-Purpose Registers (GPRs)
• generic intrinsics (1), (2)
• get commands
• glossary
• GPRegs
• GPRs (general-purpose registers)
• GPRs (General-Purpose Registers)
• Graphical User Interface
• graphics rounding mode
• GUI buttons

• HBR (hint for branch)
• hint for branch (HBR)
• hint-trigger address

• I/O devices (1), (2)
• IBM Full System Simulator, dynamic timing analysis
• IBM Full System Simulator for the Cell Broadband Engine (1), (2)
• IDL (Interface Definition Language)
• IEEE 754 (1), (2)
• in-order (1), (2), (3), (4)
• instruction types (1), (2)
• inter-loop dependencies
• Interface Definition Language (IDL)
• intrinsics (1), (2), (3), (4), (5)
• intrinsics, casting
• intrinsics, not available as generic intrinsics

• Joint Software Reference Environment (JSRE)
• JSRE (Joint Software Reference Environment)

• link register (LR)
• Linux command prompt
• Linux mode
• Linux task
• Linux threads
• list element
• Load-Exec
• local store domains
• loop-carried dependencies
• loop unrolling
• loop-unrolling
• LR (Link Register)
• LS considerations

• M:N thread model
• macro translation
• macros (MFC), input and output
• mailboxes (queues)
• main storage domain
• many-to-one signaling
• mapping PPE to SPEs
• Memory Flow Controller (MFC) (1), (2)
• memory use (limitation of)
• method stub
• MFC (Memory Flow Controller) (1), (2)
• MFC command-parameter registers
• microthreads
• model instruction
• model pipeline
• monitoring performance
• multi-stage pipeline model
• multibuffering (1), (2)

• NaN (not-a-number)
• non-blocking channel
• not-a-number (NaN)

• one-to-one signaling
• overlays

• packed operands
• parallel-array form
• parallel-stages model
• partitioning
• PCAddressing
• PCC Core window
• PCCCore
• PCTrack
• performance, SPU
• performance of microprocessors (1), (2)
• performance simulation
• performance statistics, displaying
• pipeline mode
• porting SIMD code from PPE to SPEs
• power use (limitation of)
• PowerPC Architecture Vector/SIMD Multimedia Extension
• PowerPC instructions
• PowerPC Processor Element (PPE) (1), (2), (3), (4)
• PPE, and the SPEs
• PPE (PowerPC Processor Element)
• PPE and SPE, architectural differences
• PPE-centric models
• PPE code, parallelize for execution across multiple SPEs
• PPE code, porting for execution on SPE
• PPE instruction set
• PPE registers
• PPE thread
• ppu-gdb
• precise trap
• precision
• predicate intrinsics
• predication
• preferred slot (1), (2)
• problem-state registers
• procedures, running on the SPEs
• processor frequency (limitation of)
• profile checkpoints
• programming
• programming Models
• programming tips
• put commands

• registers
• remote procedure call (RPC) model (1), (2)
• rounding result
• RPC (remote procedure call) (1), (2)
• runtime environment

• saturation
• scalar code, programming example
• scalar intrinsics (PPE-specific)
• scalar loads
• scalar operands
• scatter-gather
• SDK (software development kit)
• Segment Lookaside Buffer
• select-bits (selb) instruction
• select-bits intrinsic
• service model
• SFP (SPU Floating-Point Unit)
• shared-memory multiprocessor model
• signal notification
• signal-notification channels
• signal-notification facility (SPE)
• signals (1), (2)
• SIMD (single-instruction, multiple-data vectorization)
• SIMD code, porting from PPE to SPEs
• SIMDization
• SIMDize
• simulation
• simulation panel
• simulator basics
• simulator command window
• simulator for the Cell Broadband Engine
• simulator prompt
• single-instruction, multiple-data vectorization (SIMD)
• SOA (structure of arrays) (1), (2)
• software development kit (SDK)
• Sony, Toshiba, and IBM (STI)
• SPE (Synergistic Processor Element) (1), (2)
• SPE-centric model
• spe_context_create
• spe_context_run
• SPE overlays
• spe_program_load
• SPE programming
• SPE thread (1), (2)
• specific intrinsics (1), (2)
• SPU (Synergistic Processor Unit)
• SPU Floating-Point Unit (SFP)
• spu-gdb
• SPU Instruction Set Architecture (SPU ISA)
• SPU intrinsics
• SPU ISA (SPU Instruction Set Architecture)
• spu_mffpscr intrinsic
• spu_mtfpscr intrinsic
• SPU performance
• spu_timing, static timing analysis
• spu-timing, static timing analyzer
• SPUChannel
• SPUCore
• SPUMemory
• SPUStats
• SPUTrack
• standalone mode
• static branch prediction
• static timing analysis, spu_timing
• STI (Sony, Toshiba, and IBM)
• sticky bit
• storage barriers
• storage domains
• streaming model
• structure of arrays (SOA) (1), (2)
• stub
• suffixes
• synchronization commands
• Synergistic Processor Element (SPE) (1), (2), (3)
• Synergistic Processor Elements (SPEs) (1), (2)
• Synergistic Processor Unit (SPU)

• tag groups (DMA command)
• tag manager
• task
• Tcl (Tool Command Language) commands
• thread (1), (2)
• thread model
• thread model (M:N)
• timing analysis
• timing simulation
• Tool Command Language (Tcl)
• transfer elements (1), (2)
• truncation

• unified register file
• unmappable Constructs
• user-mode thread model
• user threads

• vector
• vector-across form
• vector data types
• Vector instructions in PPE program, example of
• vector intrinsics
• vector multimedia registers (VMRs)
• vector operands
• vector save register (VRSAVE)
• vector/SIMD multimedia extension intrinsics
• Vector/SIMD Multimedia Extension vector types
• vector/SIMD multimedia extensions (1), (2), (3)
• vector status and control register (VSCR)
• vector types
• vectorization
• VMRs (vector multimedia registers)
• VRSAVE (vector save register)
• VSCR (vector status and control register)

• XER (fixed-point exception register)

• zero result